(1) Field of the Invention
The invention relates to testing the performance of a built-in self-test (BIST) circuit, and more particularly, to a method and an apparatus for testing the performance of a BIST circuit in detecting faults in an embedded memory during the design phase.
(2) Description of the Prior Art
As deep sub-micron ASIC and IC technology evolves, greater numbers of IC devices are being designed and fabricated with embedded memories. Consequently, the industry requires an automated test strategy for embedded memories. Device testing requires a mechanism to apply a stimulus to a device under test, to acquire the device's response, and to analyze and compare that response with a known good (non-faulty) response. Classical IC testing procedures utilize external test patterns as the stimulus. These patterns are applied to the device under test using an automated tester. The tester examines the device response to stimulus and compares it against the known good response that has been stored in the tester as part of the test pattern data.
Another approach to verifying the corrected operation of an integrated circuit device is the built-in self-test (BIST) circuit. BIST circuits place the function of the external, automated tester within the IC chip itself. In a BIST circuit, a finite state machine (FSM) is used to generate stimulus and to analyze the response of the part of the integrated circuit that is under test. The BIST circuitry interfaces also with the higher-level system.
Referring now to FIG. 1, a block-level arrangement of a BIST circuit 10 and an embedded memory 14 is shown. The system-level input and outputs are DIN 15, DOUT 16, TEST 19, and STATUS 20. DIN 15 and DOUT 16 are byte-wide or word-wide data buses, including access control signals, used by the integrated circuit system. Under normal operating conditions, the TEST signal 19 is in the inactive state. In this condition, the BIST circuit 10 is bypassed and the system has direct access to the embedded memory data through data buses BDIN 17 and BDOUT 18.
During test mode, however, the TEST signal 19 is activated. In this mode, the BIST circuit 10 has access to the embedded memory 14. The BIST circuit 10 can run a self-test function and provide a pass/fail indication and “test done” indication back to the system through the STATUS signal 20.
It is very important that the BIST circuit design and algorithm accurately detect faults in the embedded memory. The BIST circuit must therefore be systematically verified. Circuit design and verification for a traditional hardware circuit is illustrated in FIG. 2. The traditional circuit design process may begin at a high level wherein functional blocks are created and linked together. The design proceeds to the register transfer level (RTL) 22 wherein time data bus processing of byte wide or word wide data is reflected in the design. The RTL design 22 is then synthesized 24 to a gate level design 32. At the gate level, individual logic gates are used to form the various registers and random logic used to create the circuit.
At the gate level 32, it is possible to carry out traditional verification 28. In a traditional verification scheme, the gate level 32 circuit schematic is entered into a computer-aided design (CAD) program so that a netlist can be generated for computer simulation. Test patterns 36 can then be generated in a simulation tool. Simulations 40 are run using the gate level circuit. The performance of the gate level design 32 can thereby be tested using a set of test patterns 36. Further, the rigorousness of the test patterns 36 themselves can be evaluated by fault grading the patterns against the circuit design using traditional “stuck at” faulting of nodes within the gate level design 32.
However, it is found that the traditional hardware design flow of FIG. 2 is not sufficient for verifying the performance of a BIST circuit in detecting faults within the embedded memory. This insufficiency stems from the fact that the BIST circuit, itself, generates the test patterns. Therefore, the designer losses the ability to tailor the patterns to detect memory faults. A new design verification method for BIST circuits and embedded memory is needed.
Several prior art inventions describe BIST circuits and methods. U.S. Pat. No. 6,012,157 to Lu teaches a system to evaluate the effectiveness of a BIST controller by simulation. Lu does not address scrambling and descrambling physical and logical addresses. U.S. Pat. No. 5,822,228 to Irrinki et al discloses a method for measuring propagation delays of embedded cores and of integrated circuits. A BIST generator and a test compactor are used to simulate the device and to latch results. U.S. Pat. No. 5,513,339 to Agrawal et al teaches a method to simulate a circuit containing both logic gates and memory blocks to determine fault detection. Concurrent simulation and record removal are used to speed up the simulation. U.S. Pat. 5,475,624 to West discloses a method to aid development of fault detection test patterns using emulators. A ‘good’ emulator and a ‘faulted’ emulator are exercised with the same test pattern to test the pattern's effectiveness at detecting faults.
J. Dreibelbis, et al, ‘Processor-Based Built-In Self-Test for Embedded DRAM,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 11, November 1998, pp. 1731–1740, teaches a BIST circuit wherein additional flexibility is achieved through the use of processor elements, such as an instruction counter, a instruction memory, and a branch controller. “Built-In Self-Test (BIST) Using Boundary Scan,” Texas Instruments Corp., December 1996, pp. 1–8, discloses a boundary scan test architecture that supports BIST. I. Burgess, “Test and Diagnosis of Embedded Memory Using BIST,” Mentor Graphics Corp., September 2000, pp. 1–6, teaches an augmentation to a BIST controller to enable a scan out of failed memory data to aid in diagnosis.